Agile Hardware Specialization: A toolbox for Agile Chip Front-end Design

Overview

Compared to software design, hardware design is more expensive and time-consuming. This is partly because software community has developed a rich set of modern tools to help software programmers to get projects started and iterated easily and quickly. However, the tools are seriously antiquated and lacking for hardware design. Modern digital chips are still designed manually using hardware description language such as Verilog or VHDL, which requires low-level and tedious programming, debugging, and tuning. In this tutorial, we will introduce Agile Hardware Specialization (AHS) : A toolbox for Agile Chip Front-end Design.

The tutorial will highlight the methodology and open source tools in AHS for both chip design and verification. From the design perspective, AHS present three ways that use different programming interfaces and target different scenarios, including; 1) a multi-level hardware intermediate representation based high-level synthesis flow, which uses C and C++ as the programming language; 2) an embedded hardware description language, which uses Rust as the programming language; 3) a large language model (LLM)-powered hardware design flow, which uses natural language as the programming language. These three different methodologies exhibit different trade-offs in productivity and PPA (performance, power, and area) for chip design. From the verification perspective, we will present agile simulation and debugging tools, which can check the functional and performance behaviors of the hardware. The attendees will learn the methodology, design automation fundamentals, and software tools of AHS.

Setup

We provide both Docker and local setup. See Environment Setup page for details.

Schedule

The tutorial will be held at Monday, 31 March 2025 (11:00 CEST - 12:30 CEST).

Detailed Program

• Part 1: Lecture (1 hour)

• Part 2: Hands-on session (30 mins)

Repos and Publications

Framework	Repository	Materials
POPA	pku-liang/popa	FPGA’24 Paper, FCCM’23 Paper
Hector	pku-liang/Hector	ICCAD’22 Paper
Hestia	pku-liang/hestia	MICRO’24 Paper
Cement	pku-liang/Cement	FPGA’24 Paper, Crates.io Package, Documentation
OriGen	pku-liang/OriGen	ICCAD’24 Paper, Hugging Face
Khronos (ksim)	pku-liang/ksim	MICRO’23 Paper

Contents:

• Handout
  • Handout Materials
    • Environment Setup
    • Reading Materials
• Tutorial Instructions
  • Cement instructions
    • Cement Example Contents
    • Running Cement Examples
    • Simulation with Khronos
  • Khronos instructions
    • Khronos Command Cheet Sheet
    • Compilation Workflow of Khronos
    • Intermediate Representations in Khronos
    • Real Application Evaluation
  • Origen instructions
    • Website
    • Examples